Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers

17 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 349-354
https://doi.org/10.1109/memsys.1994.556165

Abstract

This paper presents an approach to build electronic systems with very high chip count. Instead of packing the chips laterally as it is done in multichip-modules (MCMs), individual dies, blocks of dies and ultimately entire wafers are stacked on top of each other. Electrical interconnection is accomplished using plated through-hole contacts through the silicon substrate. Proper thermal management is obtained using dedicated heat distribution contacts, which can be fabricated by a judiciously designed mask layout and without additional processing effort. Thermally induced stress in the interconnections between the stacked layers is limited both by means of design and process variations.

Keywords

This publication has 1 reference indexed in Scilit:

Straight Wall Bumps for High Lead Count Devices: Photolithography and Physical Properties.
MRS Proceedings, 1989