Delay insensitive micro-pipelined combinational logic
- 31 October 1993
- journal article
- Published by Elsevier in Microprocessing and Microprogramming
- Vol. 36 (5) , 225-241
- https://doi.org/10.1016/0165-6074(93)90262-j
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- An asynchronous approach to the RISC design of a micro-controllerMicroprocessing and Microprogramming, 1993
- A formal approach to designing delay-insensitive circuitsDistributed Computing, 1991
- MicropipelinesCommunications of the ACM, 1989
- A formal model for defining and classifying delay-insensitive circuits and systemsDistributed Computing, 1986