High-Speed Power Flows Using Attached Scientific ("Array") Processors
- 1 January 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Apparatus and Systems
- Vol. PAS-101 (1) , 249-253
- https://doi.org/10.1109/TPAS.1982.317345
Abstract
The array processor is a comparatively recent innovation in computer architecture which promises large amounts of inexpensive computing power on fairly large problems. In particular, it is able to handle problems involving large, sparse matrix manipulations without serious degradation in performance. One such problem is the AC Power Flow simulation. This paper describes the implementation of Stott's Fast Decoupled Power Flow algorithm on the Floating Point Systems AP-120B array processor. The goal is a power flow which will solve a 1000-bus problem in less than 0.5 second from a "flat start". The parallelism afforded by the functional units of the AP- 120B have a pronounced effect on how the algorithm is implemented. The sparse linear equation solver dictates the hardware options with which the AP-120B should be equipped.Keywords
This publication has 7 references indexed in Scilit:
- Application Of An Array Processor For Power System Network ComputationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A Computation Model of Parallel Solution of Linear EquationsIEEE Transactions on Computers, 1980
- Optimal Decomposition of Large-Scale NetworksIEEE Transactions on Systems, Man, and Cybernetics, 1979
- Parallel Processing of Power System Analysis Problems Via Simple Parallel Microcomputer StructuresIEEE Transactions on Power Apparatus and Systems, 1978
- An efficient heuristic cluster algorithm for tearing large-scale networksIEEE Transactions on Circuits and Systems, 1977
- Fast Decoupled Load FlowIEEE Transactions on Power Apparatus and Systems, 1974
- Some Basic Techniques for Solving Sparse Systems of Linear EquationsPublished by Springer Nature ,1972