A fault simulator for MOS LSI circuits

1 June 1988

proceedings article
Published by Association for Computing Machinery (ACM)

p. 436-445
https://doi.org/10.1145/62882.62935

Abstract

This paper describes a fault simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. The simulator provides the capability of modeling and simulating both the classical input/output stuck-at faults and the nonclassical transistor stuck-on and stuck-open faults.

Keywords

BASIC PRIMITIVE
OUTPUT STUCK-AT FAULT
NON-CLASSICAL TRANSISTOR STUCK-ON
CLASSICAL INPUT
STUCK-OPEN FAULT
MOS TRANSISTOR STRUCTURE
FAULT SIMULATOR
MOS LSI CIRCUIT
INPUT OUTPUT
MODELING AND SIMULATION
LOGIC GATES
COMPUTATIONAL MODELING
LOGIC CIRCUITS

This publication has 3 references indexed in Scilit:

A multiple delay simulator for MOS LSI circuits
Published by Association for Computing Machinery (ACM) ,1980
Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits
Bell System Technical Journal, 1978
Analysis of actual fault mechanisms in CMOS logic gates
Published by Association for Computing Machinery (ACM) ,1976