Optimal order of the VLSI IC testing sequence

1 January 1986

proceedings article
Published by Association for Computing Machinery (ACM)

p. 560-566
https://doi.org/10.1145/318013.318103

Abstract

In this paper we introduce a technique which manipulates the order of tests to minimize the length of the testing sequence. Probabilities of fault occurrences which are analyzed in terms of random phenomena inherent in VLSI manufacturing process are used to determine this optimal testing order. Simulation of the PLA testing process indicates that there exist possibilities for the significant improvement in testing efficiency of the actual VLSI circuit.

Keywords

VLSI IC TESTING SEQUENCE
VLSI MANUFACTURING PROCESS
RANDOM PHENOMENON
FAULT OCCURRENCE
OPTIMAL ORDER
TESTING SEQUENCE
OPTIMAL TESTING ORDER
ACTUAL VLSI CIRCUIT
PLA TESTING PROCESS
SIGNIFICANT IMPROVEMENT
MANUFACTURING
VERY LARGE SCALE INTEGRATION
RANDOM TESTING

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