A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

This publication has 2 references indexed in Scilit:

• RF/wireless interconnect for inter- and intra-chip communications
  Proceedings of the IEEE, 2001
• A monolithic 2.3 Gb/s 100 mW clock and data recovery circuit
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1993