Architectural considerations for a sub 10 nanosecond DSP building block family

24 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 11, 417-420
https://doi.org/10.1109/icassp.1986.1169048

Abstract

A recently announced bipolar VLSI fabrication process provides high-speed ECL gates with substantially lower power dissipation and smaller device sizes. This combination can implement a 16 × 16 bit multiplier array with a delay time of less than 10 nanoseconds, less than 2 watts power dissipation and a silicon area comparable to 1.5 micron CMOS of 16.3K sq. mils. This paper will discuss the architectural considerations of applying this new technology to a family of fixed-point VLSI building blocks for digital signal processing applications.

Keywords

DIGITAL SIGNAL PROCESSING
VERY LARGE SCALE INTEGRATION
PACKAGING
PINS
STRONTIUM
DELAY EFFECTS
POWER DISSIPATION
CMOS TECHNOLOGY
INTEGRATED CIRCUIT TECHNOLOGY
PRODUCTION

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