Design and implementation of an ordered memory access architecture
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 345-348 vol.1
- https://doi.org/10.1109/icassp.1993.319126
Abstract
The authors describe a multiprocessor machine for real-time digital signal processing that uses commercial programmable DSP chips. The architecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled. The design is based on the architecture proposed by J.C. Bier and the authors (1990). A prototype has been built. The implementation details and performance results are discussed.<>Keywords
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