A video rate two dimensional FFT processor

24 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 5, 774-777
https://doi.org/10.1109/icassp.1980.1170966

Abstract

This paper describes a parallel high speed multiprocessor architecture suitable for realizing a 512×512 point 2-D FFT in under 1/30 of a second; enabling real time video display processing. The hardware employs a constant geometry algorithm for the implementation and utilizes 16 butterfly processors. The machine can be described as a Multiple Instruction Multiple Data (MIMD) type of machine since 16 processors will be working on 16 sets of data simultaneously. The memory organization is modular in design and provides conflict-free access to all 16 processors at all times. The memory can be interfaced to a host computer which can do other nonreal time picture processing operations on the transformed image.

Keywords

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