A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 219-220
https://doi.org/10.1109/vlsic.2001.934245

Abstract

Describes a novel power-supply scheme suitable for 0.5V operating LSIs. The system contains the on-chip buck dc-dc converter with over-90% efficiency, 0.5V operating logic, 100MHz operating F/Fs with holding data in the stand-by mode, and the dual-rail level converter. The dc-dc converter TEG, fabricated using 0.35/spl mu/m multi-Vt SOI CMOS process, realized stable recovery characteristics and a final stage efficiency of 92% with 0.5V/10mW output.

Keywords

CMOS TECHNOLOGY
LARGE SCALE INTEGRATION
DC-DC POWER CONVERTERS
BATTERIES
POWER GENERATION
INVERTERS
OPERATIONAL AMPLIFIERS
CLOCKS
BREAKDOWN VOLTAGE
REGULATORS

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