An Efficient Channel Router
- 1 January 1984
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a spcified net list between two rows of terminals across a two layer channel. This paper presents a new routing algorithm, which is an improved version of the classical "left edge algorithm". The new algorithm uses a row by row approach, calculating an optimum net assignment to each row. The algorithm was implemented for examples in previously published papers. Experimental results show that the new algorithm produces optimum solutions in most cases.Keywords
This publication has 4 references indexed in Scilit:
- Hierarchical Channel RouterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Efficient Algorithms for Channel RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982
- A “greedy” channel routerPublished by Association for Computing Machinery (ACM) ,1982
- A “Dogleg” channel routerPublished by Association for Computing Machinery (ACM) ,1976