Experiment to investigate self-testing techniques in VLSI

1 January 1985

journal article
Published by Institution of Engineering and Technology (IET) in IEE Proceedings G (Electronic Circuits and Systems)

Vol. 132 (3) , 105-107
https://doi.org/10.1049/ip-g-1.1985.0022

Abstract

The paper contains the results of an experiment which observes the capabilities of a linear feedback shift register network, to both generate pseudorandom test patterns and compress the results of a test. Two typical networks from an actual LSI designed machine are used.

Keywords

LSI DESIGNED MACHINE
IC TESTING
LINEAR FEEDBACK SHIFT REGISTER NETWORK
COMBINATIONAL NETWORKS
LOGIC CIRCUITS
SELF-TESTING TECHNIQUES
PSEUDORANDOM TEST PATTERNS
PATTERN GENERATION
VLSI