An advanced optimizer for the IA-64 architecture
- 1 January 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 20 (6) , 60-68
- https://doi.org/10.1109/40.888704
Abstract
The IA-64 architecture has a rich set of features including control and data speculation, predication, large register files, and an advanced branch architecture, which allow the compiler to exploit instruction-level parallelism (ILP) and optimize applications in many new ways. The Intel IA-64 compiler incorporates i) state-of-the-art optimization techniques known in the compiler community, ii) optimization techniques that are extended to exploit the resources and features in IA-64, and iii) new optimization techniques designed for IA-64.Keywords
This publication has 9 references indexed in Scilit:
- Data flow and dependence analysis for instruction level parallelismPublished by Springer Nature ,2006
- The Intel IA-64 compiler code generatorIEEE Micro, 2000
- Introducing the IA-64 architectureIEEE Micro, 2000
- The IA-64 architecture at workComputer, 1998
- A new algorithm for partial redundancy elimination based on SSA formPublished by Association for Computing Machinery (ACM) ,1997
- Compiler technology for future microprocessorsProceedings of the IEEE, 1995
- Compiling for the CydraThe Journal of Supercomputing, 1993
- The multiflow trace scheduling compilerThe Journal of Supercomputing, 1993
- Instruction-level parallel processing: History, overview, and perspectiveThe Journal of Supercomputing, 1993