Photoelectrochemical plating of via GaAs FET's

1 January 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 5 (1) , 7-9
https://doi.org/10.1109/edl.1984.25811

Abstract

A new photoelectrochemical (PEC) technique for filling via holes in GaAs FET's with a solid deposit of metal, such as gold, has been developed. Photogenerated electrons reduce solvated Au(CN)2-, directly on the FET source pads, allowing narrow straight-walled plasma-etched via holes to be filled without forming voids. The photogenerated holes cause the decomposition of a small amount of the semi-insulating (SI) substrate. With illumination from a 1200-W tungsten-halogen lamp, plating rates of 0.8 µm/min over a 2-in-diam wafer are achieved. The plating rate is insensitive to Au(CN)2- concentration in the range 0.01 to 0.15 M. The resulting GaAs FET's show improved mechanical stability and thermal resistance.

Keywords

This publication has 0 references indexed in Scilit: