A VHDL standard package for logic modeling
- 1 June 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 7 (3) , 25-32
- https://doi.org/10.1109/54.56464
Abstract
A package facility that enables designers to write models intuitively, without being forced to work with the underlying complexity and verboseness of the base VHDL (VHSIC hardware description language), is described. The VHDL environment handles all technology-dependent calculations automatically and drops in the lookup tables and utility function code as appropriate. In addition, the VHDL package facility automatically inserts the bus-resolution function where required, avoiding any need for the hardware designer to code or see this complex function. The package conforms strictly to the IEEE 1076-1987 specification and is therefore portable to a wide range of VHDL environments.Keywords
This publication has 5 references indexed in Scilit:
- Switch-level VHDL descriptionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- VHDL: a call for standardsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The VHDL HandbookPublished by Springer Nature ,1989
- VHDL: Hardware Description and DesignPublished by Springer Nature ,1989
- An Algebra for Logic Strength SimulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983