Design for a high-speed m.o.s. associative memory

27 July 1972

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 8 (15) , 391-393
https://doi.org/10.1049/el:19720285

Abstract

An experimental 64-bit m.o.s. associative memory has been developed from a limit-case design study. Speeds in excess of 50 MHz are reported at a cost per bit that could approach eight times that for a conventional m.o.s. dynamic r.a.m. The design of the basic associative memory cell is described.

Keywords

ASSOCIATIVE STORAGE
SEMICONDUCTOR STORAGE SYSTEMS
HIGH SPEED MEMORY
50 MHZ
CELLULAR ARRAYS
LIMIT CASE DESIGN
RANDOM ACCESS STORAGE
MOS

This publication has 0 references indexed in Scilit: