An efficient scheme for interprocessor communication using dual-ported RAMs

1 October 1989

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro

Vol. 9 (5) , 10-19
https://doi.org/10.1109/40.45822

Abstract

An approach for interprocessor interconnection is described in which communication between the processor nodes involves writing into and reading from a common memory area. The communicating processors do not have to contend for a common bus as in the case of shared-memory systems, since they have independent access to the common memory units shared between them. Only the memory access time of the processors limits the communication speed. Processor-to-processor communication does not use intermediate buffers, input/output ports, or DMAs. The example of a three-dimensional cube is used to illustrate the advantages of this scheme. The implementation of the interprocessor communication scheme on a 64-node cube configuration is discussed.

Keywords

This publication has 3 references indexed in Scilit:

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