A practical method for reducing the effects of parasitic capacitances in integrated circuits

1 January 1967

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE

Vol. 55 (2) , 235-236
https://doi.org/10.1109/PROC.1967.5458

Abstract

In integrated circuits, effects of distributed junction capacitance associated with the diffused resistor structure can be reduced by isolating this capacitance from the ac ground. In this letter a pactical method of obtaining is such an isolation is proposed and analytical results are presented to verify iprovement in high frequency performance.

Keywords

PARASITIC CAPACITANCE
PROTONS
PHOTOVOLTAIC CELLS
SILICON
DEGRADATION
CONDUCTIVITY
ELECTRONS
IMPURITIES
PHOTOVOLTAIC SYSTEMS
SOLAR POWER GENERATION

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