Methods Used in an Automatic Logic Design Generator (ALERT)
- 1 July 1969
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-18 (7) , 593-614
- https://doi.org/10.1109/t-c.1969.222727
Abstract
The ALERT system converts preliminary high-level descriptions of computers into logic. The input to ALERT depicts the architecture of a proposed machine in a form of Iverson notation. As output, the architecture is "compiled" into Boolean equations, which may then be converted into standard computer circuits.Keywords
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