A 24 Mbit/s 1,7 read channel combo for disk-drive applications
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 10.1.1-10.1.4
- https://doi.org/10.1109/cicc.1993.590686
Abstract
A BiCMOS low-power, 5-V, single-chip read channel IC is presented. This device contains all the functional blocks needed to implement a high-performance read channel, including the AGC (automatic gain control) programmable active filter, pulse detector, servo demodulator, data separator, and time base generator. External components are minimized for small-form factor evolution and cost reduction. This versatile device supports 8-24 Mb/s data rate operation in 1,7 RLL format. It also supports constant density recording. Typical power dissipation is 400 mW. The programmability, testability, and configuration of this device are achieved by a bidirectional serial microprocessor interface and internal registers.Keywords
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