Monolithic multiplier/divider

1 January 1979

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXII, 230-231
https://doi.org/10.1109/isscc.1979.1155930

Abstract

A monolithic analog multiplier/divider circuit which achieves less than 0.03% FS nonlinearity error with a large signal bandwidth of 3MHz will be reported. Design also incorporates nonlinearity compensation.

Keywords

NONLINEAR EQUATIONS
RESISTORS
VOLTAGE
BANDWIDTH
CIRCUIT SYNTHESIS
GEOMETRY
DIFFERENTIAL AMPLIFIERS
BIPOLAR TRANSISTORS
COSTS
FABRICATION

This publication has 1 reference indexed in Scilit:

A precise four-quadrant multiplier with subnanosecond response
IEEE Journal of Solid-State Circuits, 1968