Process considerations in restructurable VLSI for wafer-scale integration

1 January 1984

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1984.190800

Abstract

Wafer-scale integration has recently been demonstrated using a technique called Restructurable VLSI. An array of logic cells embedded in programmable interconnect is fabricated on the wafer. All the parts are tested by wafer probing, and links are made or broken with a laser to wire the complete system. One such chip, a digital integrator 24 cm2in area with 25 MHz input data rate, has been successfully programmed. This paper will describe the RVLSI concept and discuss several aspects of wafer fabrication which are unusual in this technology.

Keywords

VERY LARGE SCALE INTEGRATION
WAFER SCALE INTEGRATION
INTEGRATED CIRCUIT INTERCONNECTIONS
PROGRAMMABLE LOGIC ARRAYS
INSULATION LIFE
TESTING
LASER BEAM CUTTING
PROBES
OPTICAL DEVICE FABRICATION
READ-WRITE MEMORY

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