The design of an asynchronous MIPS R3000 microprocessor

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23 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 164-181
https://doi.org/10.1109/arvlsi.1997.634853

Abstract

The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 /spl mu/m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.

Keywords

MICROPROCESSORS
DELAY
ASYNCHRONOUS CIRCUITS
PIPELINES
THROUGHPUT
ROBUSTNESS
ENERGY CONSUMPTION
LOW VOLTAGE
COMPUTER SCIENCE
CMOS TECHNOLOGY

This publication has 1 reference indexed in Scilit:

The Limitations to Delay-Insensitivity in Asynchronous Circuits
Published by Springer Nature ,1990