(HgCd)Te–SiO2 interface structure

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Abstract
Low‐temperature chemical vapor deposited (CVD) SiO2 has proven to be a very important material for use as a passivation on HgCdTe, principally because it combines a high resistivity and low‐temperature application with excellent interface electronic structure. As previously reported, capacitance measurements show no frequency dispersion, and NSS minima below 1×1010 cm−2 eV−1 have been realized.1 We report here on an investigation of the composition and structure of the interface between PHOTOX■ SiO2 and HgCdTe. Wafers of zone melt HgCdTe, with x=0.3 and coated with PHOTOX■ SiO2, were analyzed with simultaneous Auger electron spectroscopy (AES) and Ne ion milling. The surface of the wafer was also studied with AES and surface ellipsometry before the SiO2 was deposited. Ellipsometry indicates the presence of a thin film on the HgCdTe due to the surface treatment, with thicknesses which vary between 10 and 20 Å from wafer to wafer. The AES measurements indicate a Te count rate similar to that in bulk HgCdTe, plus significant oxygen signal, indicating the thin film is predominantly Te‐oxide. Sputter‐Auger SiO2 on HgCdTe shows an interface region width of ∼50 Å. The dominant signals from this region are Si, O, and Te. The Te line shift indicates that an oxide is not present. We interpret this to indicate that the initial thin Te‐oxide layer has been substatially reduced, leaving an interfacial layer of Si, Te, and O betwen the applied SiO2 and HgCdTe. The increase in NSS of interfaces formed on oxide‐free HgCdTe indicate this interface layer is beneficial to device passivation.

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