Possible performance of capacitively coupled single-electron transistors in digital circuits

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Abstract
We have carried out a theoretical analysis of the possible performance of single‐electron transistors with capacitive coupling in simple logic and memory circuits. Both resistively loaded and complementary transistors have been analyzed, with a detailed account of parasitic factors including thermal fluctuations and background charge variations. The analysis shows that at optimal values of the parameters including the background charge, the maximum operation temperature is close to 0.025e2/CkB, where C is the capacitance of the smallest tunnel junction. At T∼0.01e2/CkB the parameter margins are relatively wide; for the structures with 2‐nm minimum feature size, the latter temperature is close to 77 K. A typical margin for background charge fluctuations is on the order of 0.1e; these fluctuations may be a major obstacle for practical ultradense single‐electron circuits.