Combining CTL, trace theory and timing models
- 1 January 1990
- book chapter
- Published by Springer Nature
- p. 334-348
- https://doi.org/10.1007/3-540-52148-8_28
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
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- A formal model for defining and classifying delay-insensitive circuits and systemsDistributed Computing, 1986
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- Automatic verification of finite-state concurrent systems using temporal logic specificationsACM Transactions on Programming Languages and Systems, 1986
- Automatic verification of asynchronous circuits using temporal logicIEE Proceedings E Computers and Digital Techniques, 1986
- A Calculus of Communicating SystemsLecture Notes in Computer Science, 1980