Characteristics of Destruction from Latch-Up in CMOS

1 January 1977

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 24 (6) , 2226-2229
https://doi.org/10.1109/tns.1977.4329197

Abstract

It is well known that CMOS small scale integrated (SSI) circuits will experience latch-up, when subjected to a high dose rate of ionizing radiation. However, the time required for latch-up and the characteristics of the subsequent behavior causing destruction of the device are not well known. The objectives of this study were (1) to characterize the latch-up time dependence, (2) to determine the sequence of events leading to destruction of the device, and (3) to characterize the destruction of the device. In keeping with these objectives, it was found that (1) the device does not actually latch for > 100 nanoseconds at the minimum dose rate necessary for latch-up, (2) the input protection diodes are usually involved as part of the parasitic four-layer equivalent of silicon-controlled rectifier (SCR), (3) the metallization of the VSS line (lowest potential of power source) is most orten destroyed, (4) contact window resistance increase is a prelude to metallization destruction, and (5) metallization destruction requires hundreds of microseconds.

Keywords

This publication has 2 references indexed in Scilit:

CMOS latch-up analysis and prevention
Published by Office of Scientific and Technical Information (OSTI) ,1975
Latch-Up in CMOS Integrated Circuits
IEEE Transactions on Nuclear Science, 1973