A 256K flash EEPROM using triple polysilicon technology

1 January 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVIII, 168-169
https://doi.org/10.1109/isscc.1985.1156798

Abstract

This report will cover a 256K Flash Electrically Erasable PROM with a single transistor cell. Chip size of 5.7×5.8mm²was achieved by using 2.0μ design rules and triple polysilicon technology.

Keywords

EPROM
VOLTAGE
PLASTIC PACKAGING
NONVOLATILE MEMORY
FEEDBACK CIRCUITS
ELECTRON EMISSION
NEGATIVE FEEDBACK
DIFFERENTIAL AMPLIFIERS
PROM
CIRCUIT TESTING

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