Sub-60 nm physical gate length SOI CMOS

22 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 431-434
https://doi.org/10.1109/iedm.1999.824186

Abstract

This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of silicon film thickness. A high performance SOI CMOS with well-behaved 52 nm gate length devices is demonstrated.

Keywords

THRESHOLD VOLTAGE
DESIGN OPTIMIZATION
CMOS TECHNOLOGY
BORON
DIELECTRIC SUBSTRATES
IMPLANTS
COPPER
RESEARCH AND DEVELOPMENT
SILICON ON INSULATOR TECHNOLOGY
PARASITIC CAPACITANCE

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