A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 15-ns 16-Mbit CMOS SRAM which uses a reduced voltage amplitude data bus and a hierarchical sense amplifier scheme is described. The SRAM is organized as 4 Mwords*4 bits. Fast access time and low power dissipation are obtained by a reduced-voltage-amplitude data bus connected to a latched cascaded sense amplifier and current sense amplifier. The waveforms of the address input and the data output lines at room temperature with a 3-V supply are shown. The access time is typically 15 ns, with an active current consumption of 55 mA at 3.0 V and 30 MHz.<>Keywords
This publication has 2 references indexed in Scilit:
- A 40ns 64Mb DRAM With Current-sensing Data-bus AmplifierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- An 18-ns 1-Mbit CMOS SRAMIEEE Journal of Solid-State Circuits, 1988