A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy
- 1 January 1990
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a supply voltage of -5.2 V. An access time of 7 ns has been obtained. Active 680 mW for ×4 mode. The cell size is 5.4 μm×7.2 μm (38.88 μm2); the die size is 5.46 mm×16.16 mm (88.24 mm2)Keywords
This publication has 2 references indexed in Scilit:
- An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array sizePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 14-ns 1-Mbit CMOS SRAM with variable bit organizationIEEE Journal of Solid-State Circuits, 1988