The performance impact of vector processor cashes
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. i, 437-448 vol.1
- https://doi.org/10.1109/hicss.1992.183193
Abstract
To accurately evaluate the performance impact of a vector cache, the authors simulate three vector processor designs, each of which is derived from expected technology changes applied to the Ardent Titan. The simulator is an accurate timing model incorporating the necessary aspects of the processor, cache, and memory system. It is found that current trends in memory and processor performance lead to increasingly severe memory speed and bandwidth limitations. Either of two designs using large cache memories (2MB, 4MB) on the average double processor performance relative to a design without a cache. Hit ratios for almost all of the programs used in the simulations, drawn from real Ardent workloads, are over 99%. Based on this work, it is recommended that future supercomputers incorporate large caches for both vector and scalar data.Keywords
This publication has 10 references indexed in Scilit:
- Cache performance of vector processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The Titan Graphics Supercomputer architectureComputer, 1988
- Program locality of vectorized applications running on the IBM 3090 with Vector FacilityIBM Systems Journal, 1988
- Fourier transform and convolution subroutines for the IBM 3090 Vector FacilityIBM Journal of Research and Development, 1986
- Self-sorting mixed-radix fast Fourier transformsJournal of Computational Physics, 1983
- Cache MemoriesACM Computing Surveys, 1982
- Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write ThroughJournal of the ACM, 1979
- On the Paging Performance of Array AlgorithmsIEEE Transactions on Computers, 1977
- Interference in multiprocessor computer systems with interleaved memoryCommunications of the ACM, 1976
- Organizing matrices and matrix operations for paged memory systemsCommunications of the ACM, 1969