An 0.8µm CMOS technology for high performance logic applications

1 January 1987

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 362-365
https://doi.org/10.1109/iedm.1987.191432

Abstract

This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.

Keywords

CMOS TECHNOLOGY
CMOS LOGIC CIRCUITS
OXIDATION
BORON
MOS DEVICES
IMPLANTS
THRESHOLD VOLTAGE
TESTING
LEAKAGE CURRENT
LOGIC CIRCUITS

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