A programmable digital signal processor with 32b floating point arithmetic

1 January 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVIII, 92-93
https://doi.org/10.1109/isscc.1985.1156829

Abstract

A report on a programmable DSP with 32b floating point arithmetic, 32b data path, and an extensive 32b instruction set, implemented in 1.5μ NMOS technology, will be presented. The chip contains 155,000 transistors and operates at 16MHz.

Keywords

DIGITAL SIGNAL PROCESSORS
FLOATING-POINT ARITHMETIC
RANDOM ACCESS MEMORY
CIRCUITS
DIGITAL SIGNAL PROCESSING
ADDERS
READ ONLY MEMORY
MICROPROCESSORS
READ-WRITE MEMORY
PACKAGING

This publication has 0 references indexed in Scilit: