A high-performance BICMOS Technology with double-polysilicon self-aligned bipolar devices

1 November 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 8 (11) , 509-511
https://doi.org/10.1109/edl.1987.26711

Abstract

A high-performance BICMOS technology is described which incorporates 12-GHz double-polysilicon self-aligned bipolar, fully salicided CMOS devices and 1-µm features. This process is applied to a new BICMOS gate design, called transistor feedback logic (TFL), to fabricate a divide-by-16 frequency divider with a maximum operating frequency of 364 MHz. Availability of uncompromised MOS and bipolar transistors allows a free mix of pure CMOS, pure bipolar, or BICMOS gates on the same chip.

Keywords

BICMOS INTEGRATED CIRCUITS
CMOS TECHNOLOGY
MOS DEVICES
CMOS LOGIC CIRCUITS
LOGIC DEVICES
FREQUENCY CONVERSION
LOGIC GATES
VERY LARGE SCALE INTEGRATION
PROCESS DESIGN
BORON

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