Graphical parametrised structural descriptions of VLSI devices
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 282-286
- https://doi.org/10.1109/vl.1993.269612
Abstract
This paper describes the visual programming language used for giving parametrised structural descriptions of devices in the graphical VLSI design environment VIDE (Visual Integrated Design Environment).Keywords
This publication has 7 references indexed in Scilit:
- C/sup 2/: a mixed textual/graphical environment for CPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Visual register-transfer description of VLSI microarchitecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
- Three decades of HDLs. I. CDL through TI-HDLIEEE Design & Test of Computers, 1992
- The Verilog® Hardware Description LanguagePublished by Springer Nature ,1991
- Using statecharts for hardware description and synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Designer controlled behavioral synthesisPublished by Association for Computing Machinery (ACM) ,1989
- Escher-a geometrical layout system for recursively defined circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988