Testability-preserving circuit transformations

This publication has 6 references indexed in Scilit:

• On the design of robust multiple fault testable CMOS combinational logic circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• On the design of path delay fault testable combinational circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Testing and Reliable Design of CMOS Circuits
  Published by Springer Nature ,1990
• Detection of Multiple Faults in Combinational Logic Networks
  IEEE Transactions on Computers, 1972
• On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets
  IEEE Transactions on Electronic Computers, 1966