Optimization of n+μc-Si:H contact layer for low leakage current in a-Si:H thin film transistors

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Abstract
The leakage current in a- Si:H thin film transistors(TFTs) at low drain voltages (<5 V ) and at low gate voltages (<5 V ) is observed to be due to diffusion of phosphorus into the a- Si:H layer from the n + μc- Si:H contact layer, where the phosphorus is used as an n dopant. This diffusion creates a relatively high conductivity path in the a- Si:H layer, near the n + μc- Si:H /a- Si:H interface, as well as defect states in the bulk a- Si:H region. A systematic characterization of the TFT for different deposition temperatures of the contact layer indicates that the optimal deposition temperature for low leakage current (and hence, low phosphorus diffusion) is around 200 ° C . A physical model has been developed to predict the dependence of the leakage current on voltage. Simulated and measured characteristics are in reasonable agreement.

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