Packaged 7 mW, 1.2 GHz dynamic 60/61 GaAs prescaler

27 March 1986

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 22 (7) , 355-356
https://doi.org/10.1049/el:19860241

Abstract

A 7 mW, 400 MHz–1.2 GHz GaAs low-power dual-modulus prescaler has been designed and processed, using the DCFL approach and aligned technology. Dynamic logic allows significant power reduction and minimum component count. Phase noise measurements and frequency behaviour in a silicon PLL are comparable with common frequency synthesis systems.

Keywords

DCFL
FREQUENCY SYNTHESIS SYSTEMS
MINIMUM COMPONENT COUNT
DYNAMIC LOGIC
POWER DISSIPATION 7 MW
LOW-POWER DUAL-MODULUS PRESCALER
ALIGNED TECHNOLOGY
SEMICONDUCTORS
1.2 GHZ DYNAMIC 60/61 GAAS PRESCALER
POWER REDUCTION
PHASE NOISE
FREQUENCY BEHAVIOUR

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