We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixed- signal circuits. Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation. The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits. The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples. I. INTRODUCTION As monolithic mixed-signal systems reach higher levels of inte- gration, modeling and simulating the effects of fast switching tran- sients have become increasingly important to the circuit design community. One critical issue involves the digital waveforms and their impact on the performance of sensitive analog circuitry on the same die. Noise coupling through the common chip substrate is a significant problem. Current injected across MOSFET source/drain junctions can propagate through the silicon and perturb the local substrate potential near the analog circuitry. The body effect modu- lates the threshold voltage of each transistor and, consequently, susceptible devices fail to perform as designed. The problem becomes more severe as clock rates increase, circuit features shrink, and applications demand greater precision from the analog circuitry. Substrate modeling for circuit simulation was introduced in (1), where large 3-D resistive networks were formulated to study substrate coupling in low-power RAM cells. In (2), a so-called "single node" model was developed to investigate coupling in process technologies utilizing epitaxial silicon layers on heavily- doped substrates. While this approach produced less complex equiv- alent circuit models, the scheme was inappropriate for modeling substrate interactions in a lightly-doped bulk. In (3), a localized solu- tion to Maxwell's equations based on a box integration technique was applied to the formulation of RC mesh networks representing interconnect lines and semiconductor substrates. This strategy was directly applicable to any substrate system, and in (4), was proposed as a method to study substrate-coupling in mixed-A/D circuits. In that work, the mesh-based approach was validated when results of a modeled substrate in a small example compared favorably to those obtained from device-level simulation. Later, in (5), a box-integrated substrate mesh yielded simulation results which were consistent with measurements obtained from the fabricated test circuit reported in (2). Recently, the potential applications of substrate modeling have been extended beyond transient circuit simulation. In (6), coupling effects were included in the cost function of a simulated annealing - based power distribution synthesis system, and in (7), a method to plot substrate equipotentials derived from a perturbing noise source as a function of chip position was proposed as an aid for layout plan- ning. All of the work presented to date is restricted to the generation of substrate models for small-scale analysis. In (1), (4), (5), and (7), rectangular mesh networks are generated by creating ( x,y) grid boundaries at all relevant substrate feature edges as dictated by the fabrication photomasks. In all cases , every boundary line spans a cross-section of the entire layout plane. These strategies are not prac- tical for large circuit-level analysis because the density of inter- secting x- and y- boundaries can become very high even in chip areas where the density of substrate features is small. Since the density of intersecting grid lines equals the density of nodes in the derived network model, extraneous mesh nodes are introduced in substrate regions where they are not required to obtain acceptable simulation accuracy. For any raw, lumped element substrate macromodel, some measure must be taken to reduce the mesh complexity to achieve reasonable run times with existing simulators. This is typically accomplished by formulating "equivalent" networks, in which the internal nodes have been wholly or largely eliminated, while the circuit's port characteristics remain consistent with the original. Optimal intermediate network reduction algorithms for linear mesh-