A 940 MHz data rate 8 Mb CMOS SRAM
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 198-199
- https://doi.org/10.1109/isscc.1999.759192
Abstract
An 8 Mb CMOS SRAM cycles at 470 MHz and provides a data rate of 940 MHz when run in the double-data rate (DDR) mode. Improved redundancy minimizes SRAM latency, enabling 3.4 ns access time. The HSTL I/O performance is enhanced by using flip-chip C4 packaging and by decoupling the I/O supply on-chip. The 8 Mb SRAM has an architecture to allow both /spl times/18 and /spl times/36 organizations, as well as a 4 Mb cut-down.Keywords
This publication has 2 references indexed in Scilit:
- A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 μm CMOS processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 μm CMOS processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002