A 16ns CMOS EEPLA with reprogrammable architecture

Publisher Website

1 January 1986

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 240-241
https://doi.org/10.1109/isscc.1986.1156977

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

A 50ns 48-term erasable programmable logic array
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985
An EEPROM for microprocessors and custom logic
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984