Latchup performance of retrograde and conventional n-well CMOS technologies
- 1 October 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 34 (10) , 2156-2164
- https://doi.org/10.1109/t-ed.1987.23211
Abstract
The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+epitaxial material.Keywords
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