Interface Properties of InP ‐ Dielectric Systems

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Abstract
The development of appropriate passivation schemes for III–V compound semiconductors is of considerable interest for application to high speed, high power, and electro‐optic devices and integrated circuits. In this paper, special attention is given to in connection with insulated gate technology for MISFETs applications. A review of the techniques of fabrication of systems is presented along with the main techniques of characterization developed in our group to analyze their electronic and physical properties. A detailed correlation between physicochemical properties of the interface (native oxides, phosphorus vacancies, dangling bonds,…) and electronic properties of systems (pinning of the interface Fermi‐level, drift phenomena, interface recombination processes) is presented.

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