Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

25 June 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 98-99
https://doi.org/10.1109/vlsit.2002.1015406

Abstract

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Keywords

MOSFETS
SILICON GERMANIUM
GERMANIUM SILICON ALLOYS
CMOS TECHNOLOGY
STRAIN CONTROL
ELECTRON MOBILITY
TENSILE STRAIN
COBALT
SILICIDES
DOPING

This publication has 1 reference indexed in Scilit:

Thermal and Electrical Properties of Heavily Doped Ge-Si Alloys up to 1300°K
Journal of Applied Physics, 1964