Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits

1 January 1996

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 227-232
https://doi.org/10.1109/relphy.1996.492124

Abstract

This paper presents a high ESD performance NPN protection structure for advanced submicron BiCMOS and Bipolar processes. Using a Zener trigger circuit and a specific multi-emitter layout technique, this paper successfully demonstrates an optimal protection structure to meet the requirements imposed on advanced submicron circuit applications. The protection circuit has a low trigger voltage as well as a low capacitance load and does not add any series resistance.

Keywords

ELECTROSTATIC DISCHARGE
BICMOS INTEGRATED CIRCUITS
PROTECTION
PULSE MEASUREMENTS
FINGERS
INSTRUMENTS
LOW VOLTAGE
PARASITIC CAPACITANCE
DIODES
AVALANCHE BREAKDOWN

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