A Proximity Effect Measuring Test Chip - Design And Application

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Abstract
An electrical tester has been designed for measuring proximity effect in e-beam lithography. The tester consists of a clover-shaped van der Pauw resistor for sheet resistance measurement, a four-terminal resistor for linewidth measurement, and a second four-terminal resistor of identical width but with adjacent bars for evaluating changes due to proximity exposure. The test chip is composed of a set of testers with various combinations of linewidth, bar size, and intermediate space, ranging in dimension from 0.5 μm to 10 μm. Computer software has been developed to interface a commercial computer to the wafer prober for fully automated data acquisition, statistical analysis, and graphic display. The test system yields very high precision in both the sheet resistance (3 a < 1% of nominal) and electrical linewidth (3 a < 0.01 μm). The accuracy of the linewidth data has been verified by SEM measurements. The chip can serve as a general purpose metrology tool to evaluate the efficacy of different proximity correction techniques in e-beam lithography, to complement SEM linewidth measurements which suffer from profile and threshold dependence especially for non-vertical sidewalls, and to monitor linewidth control for submicron process development. Using an e-beam exposure tool at 20kV, the chip has been delineated in GMC, a negative imaging resist, in a trilevel resist structure, on substrates of tantalum silicide and aluminum. These substrates correspond to the GATE and the METAL level substrates in a MOS integrated circuit. In addition, it has been delineated in chromium, a typical photomask substrate, using single layer resist. The extent of proximity exposure effect on each of these substrates is reported. Linewidth deviations of 0.1 μm or greater are observed for near-micron equal line and space patterns. In addition, proximity exposure increases with incident exposure dose and the atomic number of the substrate. On the basis of these results, VLSI layout constraints arising from e-beam proximity exposure are identified.

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