Titanium nitride local interconnect technology for VLSI

Abstract
This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n + and p + junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n + and p + junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils 2 feasible with 1-µm design rules, is also discussed.

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