Analog Circuit Design Optimization based on Symbolic Simulation and Simulated Annealing
- 1 September 1989
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 220, 252-255
- https://doi.org/10.1109/esscirc.1989.5468066
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- A symbolic simulator for analog circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Symbolic simulation of analog circuits in S- and Z-domainPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SAMURAI: A general and efficient simulated-annealing schedule with fully adaptive annealing parametersIntegration, 1988
- IDAC: an interactive design tool for analog CMOS circuitsIEEE Journal of Solid-State Circuits, 1987
- Noise optimization of switched-capacitor biquadsIEEE Journal of Solid-State Circuits, 1987
- A prototype framework for knowledge-based analog circuit synthesisPublished by Association for Computing Machinery (ACM) ,1987
- Optimization by Simulated AnnealingScience, 1983