A design method of systolic arrays under the constraint of the number of the processors

24 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 12, 764-767
https://doi.org/10.1109/icassp.1987.1169584

Abstract

This paper proposes a systemtic method to design systolic arrays under the constraint of the number of the processors. Our basic approach is to partition the large systolic array into the smaller number of groups, whose number is coincident with the number of processors to be used. We give the mathematical method to make at most one processor execute computation in each group. Then, each group can be replaced by one processor to satisfy the constraint of the number of the processors. Author(s) Horiike, S. Mitsubishi Electric Electronic, Amagasaki, Japan Nishida, S. ; Sakaguchi, T.

Keywords

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